The present disclosure herein relates to a semiconductor memory and, more particularly, to a memory device using an interleaving scheme.
Typically, semiconductor memory devices are classified into volatile memories such as Dynamic Random Access Memories (DRAMs) and Static Random Access Memories (SRAMs) and nonvolatile memories such as Electrically Erasable Programmable Read-Only Memories (EEPROMs), Ferroelectric Random Access Memories (FRAMs), Phase change Random Access Memories (PRAMs), Magnetoresistive Random Access Memories (MRAMs) and flash memories. Nonvolatile memories lose stored data when power supply is stopped, but nonvolatile memories retain stored data even when power supply is stopped. Particularly, flash memories have advantages of high programming speed, low power consumption, and large-capacity data storage. Accordingly, flash memory systems including flash memories are being widely used as data storage media.
Flash memories may store 1-bit data or 2 or more-bit data in one memory cell. Typically, a memory cell storing 1-bit data is called a single level cell (SLC) and a memory cell storing 2 or more-bit data is called a multi level cell (MLC). The SLC has an erase state and a program state according to a threshold voltage. The MLC has an erase state and a plurality of program states according to a threshold voltage.
In a flash memory having a multi level cell (hereinafter, referred to an MLC flash memory, a plurality of logical pages may be stored in memory cells (hereinafter, referred to as a physical page) sharing one word line. Here, each logical page may have a different bit error rate (BER). If it is assumed that the number of fail bits is identical in each reading level, an N-bit MLC flash memory may have a BER of 1:2:22: . . . :2N-1 in each logical page.